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1、外文翻译AT89C52单片机的介绍中文4800字 附录3：外文翻译 AT89C52 monolithic integrated circuit introduction AT89C52 is the low voltage which American ATMEL Corporation produces, the high performance CMOS 8 monolithic integrated circuits, internal may repeatedly scratch read-only program memory (PEROM) and 256bytes random
2、access data-carrier storage (RAM) including 8k bytes which writes, the component uses ATMEL Corporation the high density, the non-volatility memory technology production, is compatible with the standard MCS-51 command system and 8052 product pins, internal sets at general 8 central processor (CPU) a
3、nd the Flash memory cell, the function formidable AT89C52 monolithic integrated circuit suits in many comparatively plurality of controls application situation. Main performance parameter: Are completely compatible with the MCS-51 product instruction and the pin The 8k byte may again scratch writes
4、Flash to dodge the fast memory 1000 times scratches the write cycle Entire static operation: 0Hz24MHz Three level of encryption program memory 2568 In byte RAM 32 programmable I/O mouth line 3 16 fixed time/counters 8 interrupt sources Programmable serial UART channel The low power loss idle and fal
5、ls the electricity pattern Function characteristic outline: Below AT89C52 provides the standard function: 8k byte Flash dodges the fast memory, 256 byte internal RAM,32 I/O mouth line, 3 16 fixed time/counters, 6 vector two level of interrupt structures, A full-duplex serial passes unguardedly, inte
6、rnal oscillator and clock electric circuit.At the same time, AT89C52 may fall to the 0HZ static state logical operation, and supports the electricity saving working pattern which two kind of softwares may elect.The idle way stops CPU the work, but permits RAM, fixed time/the counter, serial passes u
7、nguardedly and the interruption system continues to work.Falls the electricity way to preserve in RAM the content, but the oscillator knock off and forbids other all part work to reposition until the next hardware. The pin function shows Vcc: Supply voltage GND: Grounding P0 mouth: The P0 mouth is o
8、ne group of 8 leaks leads the way extremely the bidirectional I/O mouth, also is the address/data bus multiplying mouth.As outlet with when, each potential energy absorption current way actuates 8 TTL logic gate, when writes “1” to port P0, may take the high impedance input end uses. When visits ext
9、erior data-carrier storage or the program memory, when this group of mouth line segment transforms the address (low 8) and the data bus multiplying, pulls the resistance in the visit activation interior. When Flash programming, P0 mouth receive instruction byte, but when program check, when output o
10、rder byte, verification, outside the request joins pulls the resistance P1 mouth: P1 is in a belt interior pulls the resistance 8 bidirectional I/O mouth, the P1 output buffer may actuate (absorption or output current) 4 TTL logic gate.Writes “1” to the port, pulls the resistance through internal on
11、 to pull the port to the high level, this time may make the input port.When makes the input port use, because in internal existence pulls the resistance, some pin is pulled lowly by exterior signal when can output electric current (IIL). With at89C51 similarity is, P1.0 and P1.1 also may take separa
12、tely fixed time/the counter 2 exterior countings inputs (P1.0/T2) and inputs (P1.1/T2EX), see also table 1. Flash programming and program check period, P1 receives the low 8 bit address. Table 1 P1.0 and P1.1 second function Pin number P1.0 P1.1 Function characteristic T2 (fixed time/counter 2 exter
13、ior counting pulse input), the clock outputs T2EX (fixed time/counts 2 capture/heavy loading triggering and directional control) P2 mouth: P2 is one has in the interior to pull the resistance 8 bidirectional I/O mouth, the P2 output buffer may actuate (absorption or output current) 4 TTL logic gate.
14、Writes “1” to port P2, pulls the resistance through internal on to pull the port to the high level, this time may make the input port, when makes the input port use, because in internal existence pulls the resistance, some pin is pulled lowly by exterior signal when can output electric current (IIL)
15、. When visits exterior program memory or 16 bit address exterior data-carrier storage (e.g. carries out the MOVXDPTR instruction), the P2 mouth sends out the high 8 bit address data.When visits 8 bit addresses exterior data-carrier storage (for example carries out the MOVXRI instruction), the P2 mou
16、th outputs the P2 latch the content When Flash programming or verification, P2 also receives the top digit address and some control signal. P3 mouth: The P3 mouth is a group has in the interior to pull the resistance 8 bidirectional I/O mouth.The P3 mouth output buffer may actuate (absorption or out
17、put current) 4 TTL logic gate.Reads in “1” when to the P3 mouth, they the position resistance are pulled by the interior in Gao Bingke the achievement to input the port.This time, will be pulled by the outside the low P3 mouth to use to pull resistance output current (IIL). The P3 mouth besides took
18、 the general I/O mouth line, a more important use is its second function, the following table shows: Port pin Second function P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 RXD (serial input port) TXD (serial outlet) INT0 (outside interrupts 0) INT1 (outside interrupts 1) T0 (fixed time/counter 0) T1 (fixe
19、d time/counter 1) WR (exterior data-carrier storage writes selection) RD (exterior data-carrier storage reads selection) In addition, the P3 mouth also receives some to use in Flash dodging the fast memory programming and the program check control signal. RST: Replacement input.When the oscillator w
20、orks, the RST pin will appear above two machine cycles the high level to cause the monolithic replacement. ALE/PROG: When visits exterior program memory or the data-carrier storage, ALE (address lock saves permission) to output the pulse to use in the lock saving the address the low 8 bytes.In ordin
21、ary circumstances, ALE still by clock oscilation frequency 1/6 output fixed pulse signal, therefore it may the foreign output clock or uses in fixed time the goal.Must pay attention: When visits exterior data-carrier storage will jump over a ALE pulse. To Flash memory programming period, this pin al
22、so uses in inputting programming pulse (PROG). If has the necessity, may through to in special function register (SFR) area 8EH the unit D0 position position, be possible to forbid the ALE operation.After this position position, only then MOVX and the MOVC instruction can activate ALE.In addition, t
23、his pin can pull weakly high, when the monolithic integrated circuit carries out exterior procedure, should establish the ALE prohibition position to be invalid PSEN: The procedure storage permits the (PSEN) output is exterior program memory reads the gating signal, when AT89C52 takes the instructio
24、n by exterior program memory (or data), each machine cycle two PSEN is effective, namely outputs two pulses.When visits exterior data-carrier storage, will jump over two RSEN signals. EA/VPP: Exterior visit permission.Wants to cause CPU only to visit exterior program memory (address is 0000H-FFFFH),
25、 the EA end must maintain the low level (earth).Must pay attention: If adds mil LB1 to program, when replacement the interior can lock saves the EA end condition. If the EA end (meets the Vcc end) for the high level, CPU carries out in the internal procedure memory instruction. When the Flash memory
26、 programs, this pin adds on 12V programming permission power source VPP, certainly this must be this component is uses 12V to program voltage VPP. XTAL1: Oscillator inverting amplifier and internal clock generator input end. XTAL2: Oscillator inverting amplifier out-port. Special function register:
27、In at89C52 internal memory, the 80H-FFH altogether 128 units for special function register (SFE), SFR address basement reflection as shown in Table 2. All addresses all are defined by no means, only then a part is defined from the 80H-FFH altogether 128 bytes, but also has quite a part not to define
28、.To the definition unit read-write will not have been Yuan Xiao, the read-out value will be indefinite, but will read in the data will also lose. Should not “1” not read in the data the definition unit, then will possibly entrust with the new function in these units in the future product, in this ca
29、se, after replacement these unit value always “0”. AT89C52 besides with AT89C51 all fixed time/counters 0 and fixed time/counter 1, but also increased a fixed time/counter 2.Fixed time/the counter 2 control status byte is located T2CON、T2MOD (to see Table 4), the register to (RCA02H, RCAP2L) is the
30、timer 2/automatic loads the register again under 16 capture ways or 16 automatic heavy loading way capture. Interrupt register: AT89C52 has 6 interrupt sources, 2 interrupt priorities, the IE register controls each interrupt position, in the IP register 6 interrupt source each may decide as 2 superi
31、or data-carrier storages: AT89C52 has 256 byte internal RAM,80H-FFH high 128 bytes and the special function register (SFR) address is overlap, also is high 128 byte RAM and the special function register address is same, but in physics they are separated. When an instruction visits the 7FH above dumm
32、y home address unit, in the instruction uses the addressing way is different, also is the addressing way decision is visits high 128 byte RAM to visit the special function register.If the instruction is the direct addressing way for the visit special function register. For example, following direct
33、addressing instruction visit special function register 0A0H (i.e. P2 mouth) address unit. MOV 0A0H,#data The indirect addressing instruction visits high 128 byte RAM, for example, in following indirect addressing instruction, the R0 content is 0A0H, then the visit data byte address is 0A0H, but is n
34、ot the P2 mouth (0A0H). MOV the R0,#data storehouse operation also is the indirect addressing way, therefore, high 128 bit data RAM also may take the storehouse area use. Timer 0 and timer 1: The AT89C52 timer 0 and the timer 1 working and AT89C51 are same. Timer 2: The timer 2 is 16 fixed time/coun
35、ters.It already may when timer use, also may take the external event counter use, its working chooses by the special function register T2CON C/T2 position.The timer 2 has three workings: The capture way, the automatic heavy loading (upward or downward counting) the way and the baudrate generator way
36、, the working chooses by the T2CON control position, see also table 4. Table 4 timer 2 workings PCLK+TCLK 0 0 1 CP/RL2 0 1 TR2 1 1 1 0 MODE 16-bit Auto-reload 16-bit Capture Baud Rate Generator The timer 2 is composed by two 8 register TH2 and TL2, in the timer working, each machine cycle TL2 regist
37、er value adds 1, because a machine cycle vibrates the clock constitution by 12, therefore, counting speed for oscilation frequency 1/12. When counting working, when on the T2 pin exterior input signal produces by 1 to 0 drops along, the register value adds 1, under this working, each machine cycle 5
38、SP2 period, carries on the sampling to exterior input. If picks in the first machine cycle the value is 1, but the value which picks in the next machine cycle is 0, then is following close on the next cyclical S3P1 period register adds 1.Because distinguishes 1 to need 2 machine cycles to 0 jumps (2
39、4 durations of oscillation), therefore, highest counting speed for oscilation frequency 1/24. In order to guarantee the sampling the accuracy, the request input level maintains at least before the change for a complete cyclical the time, guarantees the input signal at least by sampling one time. Cap
40、ture way: Under the capture way, chooses two ways through T2CON control position EXEN2.If EXEN2=0, the timer 2 is 16 timers or the counter, when counting overflow, to the T2CON overflow symbolized TF2 sets at the position, simultaneously activates the interrupt.If looks up EXEN2=1, the timer 2 compl
41、etes the same operation, But when the T2EX pin exterior input signal has 1 to 0 negative jumps, also appears in TH2 and the TL2 value is caught separately to in RCAP2H and RCAP2L.Moreover, the T2EX pin signal jump causes in T2CON EXF2 to set at the position, is similar with TF2, EXF2 also can interr
42、upt exactly.Capture way as shown in Figure 4. Automatic heavy loading (upward or downward counter) way: When timer 2 work in 16 automatic heavy loading ways, can to its programming for upward or the downward counting way, this function may (see Table 5) through special function register T2CON the DC
43、EN position (permission downward counting) choose.When replacement, the DCEN position “0”, the timer 2 defaults establishes as the upward counting. When DCEN sets at the position, the timer 2 already may count upwardly also may the downward counting, this is decided by the T2EX pin value, see also F
44、igure 5, when DCEN=0, the timer 2 automatic setups for the upward counting, under this way, in the T2CON EXEN2 control position have two kind of choices, if EXEN2=0, the timer 2 for the upward counting to the 0FFFFH overflow, sets at the position TF2 activation interrupt, simultaneously 16 counter r
45、egister RCAP2H and the RCAP2L heavy loading, RCAP2H and the RCAP2L value may by the software initialization. When DCEN sets at the position, the timer 2 already may count upwardly also may the downward counting, this is decided by the T2EX pin value, see also Figure 5, when DCEN=0, the timer 2 autom
46、atic setups for the upward counting, under this way, in the T2CON EXEN2 control position have two kind of choices, if EXEN2=0, the timer 2 for the upward counting to the 0FFFFH overflow, sets at the position TF2 activation interrupt, simultaneously 16 counter register RCAP2H and the RCAP2L heavy loa
47、ding, RCAP2H and the RCAP2L value may by the software initialization. Baudrate generator: When T2CON (Table 3) TCLK and RCLK set at the position, fixed time/the counter 2 takes the baudrate generator use.If fixed time/the counter 2 took the transmitter or the receiver, its transmission and the recei
48、ve baudrate may be different, the timer 1 uses in other functions, as shown in Figure 7.If RCLK and TCLK set at the position, then timer 2 work in baudrate generator way. The baudrate generator way and the automatic heavy loading way are similar, under this way, the TH2 turn over causes the timer 2
49、registers is important the new loading with in RCAP2H and the RCAP2L 16 figures, this value establishes by the software. In the way 1 and the way in 3, the baudrate determined by the timer 2 overflow speeds according to the equation below that,Way 1 and 3 baudrate = timer overflow rate /16 The timer already can work in fixed time the way also can work in the counting way, in the majority applic
