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1、August 06,PKUnity:A SoC Design and Verification Platform,August 06,Outline,PKUnity SoC Platform FeaturesMulti-Layers Verification FrameworkCDC Verification ToolFuture Works,August 06,Outline,PKUnity SoC Platform FeaturesMulti-Layers Verification FrameworkCDC Verification ToolFuture Works,August 06,W
2、hat for,Providing a PLATFORM for implementing and verifying NEW IDEALS in Nanotechnologies,Behavioral Level Simulation(SystemC),RTL Simulation/Emulation(Verilog/VHDL),FPGA Prototyping,Silicon Proving,New Ideas,Multi-MediaProcessing,CPU,On-chipcommunication,Network,Compiler,Softwares,PKUnity Platform
3、,Synthesis,Low Power,August 06,What is,PKUnity Platform includes:a scalable and configurable SoC architecturea series of UniCore CPUplenty of communication IPs a verification frameworksome verification toolscompilation tool chain and OS based on UniCore,August 06,PKUnity Architecture,UniCoreCPU,Memo
4、ry and High Speed I/O,Low Speed I/OandSystem Modules,August 06,Design Features,August 06,Design Features,CPU600MHz UniCore8-Stage Pipeline64-bit Floating Point Co-Processor16KB I/D Cache2-Port Bus Interface,Main MemoryDDR(Double Data Rate)SDRAM166MHz Clock and 64-bit Width2 Memory Access Channels,Au
5、gust 06,Design Features,High Speed I/O Devices10M/100M/1G Ethernet MAC66MHz PCI BridgeIDE SATA ControllerUSB OTG Controller,Low Speed I/O DevicesUARTI2CSPIAC97PS/2,August 06,Design Flow,SystemC-based HW/SW Co-verification,RTL Simulationand Emulation,FPGA Prototyping,Design and Implementation,RTL Sig
6、n Off,August 06,Challenges,Complex Communication ProtocolLots of Asynchronous Clock Domains,Design,Verification,&,Gap between CPU and Main MemoryDifferent Bus Bandwidth RequirementsPower Supply,August 06,Design Solutions,Two-Layer busCPU-MEM busIO-MEM bus,CPU-MEM Bus,IO-MEM Bus,Slow ClockEnough Perf
7、ormance,Reduce the power supply,Fast ClockBest Performance,Minimize CPU-MEM bandwidth gap,August 06,Verification Solutions,Multi-Layer Verification FrameworkFor Complex Communication Protocol,CDC Verification ToolFor Lots of Asynchronous Clock Domains,August 06,Outline,PKUnity SoC Platform FeaturesM
8、ulti-Layers Verification FrameworkCDC Verification ToolFuture Works,August 06,Verification Challenges,Complex Communication ProtocolAHB vs.DDR SDRAMAHB vs.PCIAHB vs.MACAHB vs.USB OTGAHB vs.IDEAPB vs.AC97,Its hard to cover all the transaction types!,August 06,Verification Methodology,Multi-LayerSigna
9、l LayerBus LayerTransaction LayerScenario Layer,August 06,Self Checking,Self Checking by two channels,August 06,Verification Framework,August 06,Example,Ethernet MAC Verification Coverage,August 06,Outline,PKUnity SoC Platform FeaturesMulti-Layers Verification FrameworkCDC Verification ToolFuture Wo
10、rks,August 06,Whats CDC,CDC:Clock Domain Crossing,August 06,Challenges,Lots of Asynchronous Clock DomainsThe relationship of clocks is static in the normal simulationIts difficult to find setup time and hold time violation(metastable state),August 06,Method(Step 1),1.Find all the CDC pathsHandshake
11、LogicGray code counter.,August 06,Method(Step 2),2.Insert a module which can provide random delays on each CDC paths,CDC_delay U_RdDMA_D(.in(RdDMAH),.out(RdDMAH_d);CDC_delay U_WrDMA_D(.in(WrDMAH),.out(WrDMAH_d);Clk_jitter U_ICLK(.in(ICLK),.out(ICLK_j);CDC_monitor U_RdDMA_M(.in(RdDMAH_d);CDC_monitor
12、U_WrDMA_M(.in(WrDMAH_d);always(posedge HCLK)begin RdDMAH=(RWCON,August 06,Method(Step 3),3.Add reasonable delays on the CDC paths in simulation repeatedly,August 06,Example,A commercial ATA-5 IDE controller IPThe table shows coverage comparability after 30 transactions finishedThe right diagram show the full coverage growth,August 06,Outline,PKUnity SoC Platform FeaturesMulti-Layers Verification FrameworkCDC Verification ToolFuture Works,August 06,Future Works,Communication ArchitectureBandwidth Allocation AlgorithmCDC Coverage Improvement,August 06,Thank You!,
